1. Field of the Invention
The present invention relates to a structure and method for configuring a field programmable gate array (FPGA).
2. Description of the Prior Art
An FPGA typically includes configuration memory cells, configuration control elements and a matrix of logic blocks and I/O blocks. To create a desired circuit, the user writes a data bit to each of the configuration memory cells. The configuration control elements are configured in response to the data bits stored in configuration memory cells. The user selects the data bits such that the configuration control elements properly configure the logic and I/O blocks to form the circuitry required by the user's design.
FIG. 1 is a schematic diagram of a prior art configuration memory cell 100 and an associated configuration control element 110. Configuration memory cell 100 includes programming transistor 101 and inverters 102 and 103. Configuration memory cell 100 is programmed using means external to the FPGA. In programming configuration memory cell 100, an enable (EN) signal is provided to the gate of transistor 101 on lead 106 and a programming (PRG) signal is provided to the source of transistor 101 on lead 107. The PRG signal is thereby transmitted through transistor 101 and stored in the latch formed by inverters 102 and 103. After the PRG signal is stored by inverters 102 and 103, the EN signal is de-asserted. As a result, the PRG signal is provided to configuration control circuit 110 on lead 104 and the inverse of the PRG signal (PRG) is provided to configuration control circuit 110 on lead 105. In response, configuration control circuit 110 provides (or prevents) an interconnection between other elements (such as logic and/or I/O blocks) in the FPGA.
The PRG signal used to program configuration memory cell 100 is a bit which is typically stored in an EEPROM, EPROM, ROM, floppy disk or hard disk which is part of the external programming means. A conventional FPGA may contain thousands of configuration memory cells like configuration memory cell 100. Programming all of these configuration memory cells requires thousands of bits. These bits are all loaded by the external programming means. When the FPGA is configured, the external programming means transmits the required bits to the FPGA in the form of a bit stream. Because this bit stream travels along a physical path from the external programming means to the FPGA, the bit stream can be accessed fairly easily by tapping into this physical path. Although copyright protection may be obtained for the bit stream, an unscrupulous copyist can nonetheless reproduce the user's device by recording the bit stream, reproducing the bit stream, and applying the bit stream to an identical FPGA. The copyist can generally obtain an identical FPGA "off the shelf" because, within a product line, FPGA's are typically manufactured in a generic manner.
Because the costs associated with designing the configuration of an FPGA-based device are significant, it would be desirable to have an FPGA which is more difficult to copy, without substantially adding to the complexity of the FPGA.